Non-volatile memory devices are memory devices that can store data when the power is cut off. Known types of non-volatile memory devices include flash memory devices, ferroelectric memory devices, phase changeable memory devices and magnetic memory devices.
Flash memory non-volatile memory devices include unit memory cells that have a structure similar to the structure of a MOS transistor. These devices do not require a separate data storage element and, as such, the cell region may be highly integrated. Generally speaking, a flash memory device may have one of two representative structures. The first such structure stores charge in a conductive floating gate, while the second representative structure stores the charge in a charge storage insulator. The flash memory devices that have the structure in which the charge is stored in a charge storage insulator may provide certain advantages, such as low program and erase voltages and excellent endurance and retention. In addition, multi-bit programmable versions of these devices can be fabricated.
FIGS. 1 through 5 depict a conventional flash memory non-volatile memory device that uses a charge storage insulator. As shown in the top plane view of the device provided in FIG. 1, the device includes a plurality of device isolation layers 28a that are formed on predetermined regions of a substrate 10 (the substrate is not shown in FIG. 1). An active region is defined between these device isolation layers 28a. A gate electrode 30 is disposed over the active region and the device isolation layers 28a. A charge trapping layer 16 is interposed between the gate electrode 30 and the active region.
FIGS. 2 through 5 are cross-sectional views taken along the line A—A of FIG. 1 illustrating various steps during the fabrication of the conventional non-volatile memory device depicted in FIG. 1. The conventional non-volatile memory device can be fabricated by forming a lower insulation layer 14, a charge trapping layer 16 and an upper insulation layer 18 on a substrate 10. A first conductive layer 20 and a hard mask layer 22 are formed on the upper insulation layer 18. The hard mask layer 22 and the first conductive layer 20 are patterned. Then, the upper insulation layer 18, the charge trapping layer 16, the lower insulation layer 14 and the substrate 10 are patterned to form the trench regions 12 that are depicted in FIG. 2.
A thermal process is then applied to the substrate 10 with the trench regions 12 to from a trench oxide layer 24 on the inner sides of the trench regions 12 (see FIG. 3). Then, an insulation layer 28 is formed on the trench oxide layer 24 to fill the trench regions 12. Generally, the substrate 10 and the first conductive layer 20 are formed of silicon. As a result, both the portion of the substrate 10 that contacts the lower insulation layer 14 and the portion of the first conductive layer 20 that contacts the upper insulation layer 18 may be partially etched (see reference numeral 26 on FIG. 3). Moreover, when silicon is thermally oxidized it expands such that it approximately doubles in volume. The tensile stress and compressive stress that results from the oxidation of the silicon substrate 10 and the first conductive silicon layer 20 may act to deteriorate the charge trapping layer 16. In addition, etch damage may occur during the formation of the trench regions 12 that leaves defects at one or both edges of the charge trapping layer 16 where the charge trapping layer 16 is aligned to the sidewalls of the trench regions 12.
As shown in FIG. 4, a chemical-mechanical polishing process may then be applied to the insulation layer 28. The insulation layer 28 is first polished until the hard mask layer 22 is exposed and the insulation layer 28 is divided into device isolation layers 28a that fill the trench regions 12. Then, the hard mask layer 22 is removed to expose the first conductive layer 20.
As shown in FIG. 5, a polysilicon layer 30 and a silicide layer 32 are then formed over the entire surface of the substrate. The polysilicon layer 30, the silicide layer 32 and the first conductive layer 20 are patterned to form a gate electrode 34 that crosses over the device isolation layers 28a. As discussed above, the conventional non-volatile memory device illustrated in FIG. 5 can have defects at the regions neighboring the device isolation layers 28a. These defects can deteriorate the data storage and endurance characteristics of the device.